1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device capable of operating with low power consumption.
2. Description of the Background Art
In recent years, semiconductor memory devices capable of being driven with low power consumption have been demanded for use in applications such as battery-powered portable equipments. In response to such a demand, the semiconductor memory devices have a low power consumption mode (power down mode) in addition to the normal mode in which normal operations such as data read operation and data write operation are required. In the low power consumption mode, most of the internal circuitry is rendered in a standby state in order to reduce the power consumption. Thus, according to an external operation request, the operation mode is switched between the normal mode and the low power consumption mode, whereby the power consumption of the semiconductor memory devices is reduced.
Since operation with a reduced voltage is effective for reduced power consumption, an external power supply voltage level has been increasingly reduced. For example, a 3.3 V-level (3.0 V to 3.6 V) external power supply voltage is used in the conventional general-purpose systems. However, a 2.7 V-level (2.7 V to 3.0 V) or 2.5 V-level (2.3 V to 2.7 V) external power supply voltage has been increasingly used in the systems operating a reduced voltage.
With reduction in power consumption, the power consumption ratio of the internal power supply circuit for generating internal power supply voltages to the entire semiconductor memory device is increased. Moreover, operation with a reduced voltage degrades the power efficiency of the internal power supply circuit. Accordingly, there is a need for a more powerful low power consumption mode in which the internal circuitry receiving the internal power supply voltages is rendered in a standby state in order to reduce not only the overall power consumption but also the power consumption of the internal power supply circuit itself.
In such a low power consumption mode as well, it is desirable that the mode entry can be implemented using an existing control system, i.e., without using a special entry method. Smooth transition to the low power consumption mode and smooth restoration to the normal mode are also desired.
As described above, various levels of external power supply voltages are currently used. In order to design the generalized semiconductor memory devices, the semiconductor memory device must be adaptable to different levels of external power supply voltages. For example, the internal power supply circuit is required to have the ability to maintain uniform control response of the internal power supply voltages even when a different level of external power supply voltage is applied.
Depending on the interface specification, the system incorporating the semiconductor memory device must be adapted to a 1.8 V-level I/O (Input/Output) signal of TTL (Transistor-Transistor Logic) level. Therefore, it is desirable that the signal input circuitry also be capable of receiving different I/O signal levels.
In the case where an operating condition to be applied is fixed in terms of the hardware by mask switching or the like in a generalized semiconductor memory device adaptable to various operating conditions (e.g., external power supply level and I/O signal level), the structure is also required that is capable of easily sensing the fixed operating condition from the outside of the semiconductor memory device.
It is an object of the invention to provide a semiconductor memory device capable of operating with low power consumption.
It is another object of the invention to provide a semiconductor memory device capable of operating with various levels of external power supply voltages and I/O signals.
It is a further object of the invention to provide, in a semiconductor memory device designed to be adaptable to various operating conditions, a structure capable of easily sensing an applied operating condition from the outside.
In summary, according to one aspect of the invention, a semiconductor memory device having a normal mode and a low power consumption mode includes: an internal circuit for conducting a data read operation, a data write operation and a data hold operation; a first external power supply line receiving a first external power supply voltage; a second external power supply line receiving a second external power supply voltage that is lower than the first external power supply voltage; an internal power supply line for transmitting an internal power supply voltage to the internal circuit; and an internal power supply circuit for receiving the first and second external power supply voltages and producing the internal power supply voltage. The internal power supply circuit includes a reference voltage generation portion for receiving the first and second external power supply voltages and generating a reference voltage corresponding to a target level of the internal power supply voltage, a first current shut-off switch for shutting off an operating current of the reference voltage generation portion in the low power consumption mode, an internal power supply voltage generation portion for keeping the internal power supply voltage at the target level according to comparison between the internal power supply voltage and the reference voltage in the normal mode, and discontinuing its operation in the low power consumption mode, and a connection switch for electrically coupling one of the first and second external power supply lines to the internal power supply line in the low power consumption mode.
Preferably, the connection switch includes an N-channel field effect transistor electrically coupled between the first external power supply line and the internal power supply line, and the first external power supply voltage is applied to a gate of the N-channel field effect transistor in the low power consumption mode.
Preferably, the connection switch includes a P-channel field effect transistor electrically coupled between the second external power supply line and the internal power supply line, and the second external power supply voltage is applied to a gate of the P-channel field effect transistor in the low power consumption mode.
In the low power consumption mode, such a semiconductor memory device can produce the internal power supply voltage without operating the reference voltage generation portion and the internal power supply voltage generation portion, allowing for reduction in power consumption of the internal power supply circuit itself.
Preferably, the semiconductor memory device further includes a mode register for retaining a mode setting that is externally applied with a first command. The mode setting includes designation of whether transition from the normal mode to the low power consumption mode is conducted or not. When the transition is designated in the mode setting, the low power consumption mode is started in response to a second command.
Thus, whether the transition to the low power consumption mode can be conducted or not can be selectively set based on the mode setting by a general mode register.
In particular, the second command is a special command for starting the low power consumption mode.
In particular, the internal circuit includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided respectively corresponding to memory cell rows and being selectively activated, and a plurality of bit lines provided respectively corresponding to memory cell columns and being respectively coupled to the memory cells corresponding to an activated word line. The second command is a refresh command for conducting the data hold operation. After the refresh command is started, the low power consumption mode is started with each of the word lines being inactivated. Thus, transition from the normal mode to the low power consumption mode can be conducted in a period other than the period during which the internal circuit is unstable.
In particular, the semiconductor memory device further includes a control circuit for instructing restoration to the normal mode according to change of an external control signal from a first level to a second level in the low power consumption mode, the external control signal being set to the first level before input of the second command.
In particular, the first level corresponds to one of the first and second external power supply voltages, and the second level corresponds to the other, and the semiconductor memory device further includes an internal control signal generation circuit for receiving the external control signal and generating an internal control signal. The internal control signal generation circuit includes a first buffer operating in the low power consumption mode and driven with the first external power supply voltage, a second buffer operating in the normal mode, for receiving the external control signal driven with the internal power supply voltage, and a logic circuit for setting the internal control signal to either the internal power supply voltage or the second external power supply voltage according to the external control signal received by one of the first and second buffers that is in operation. The control circuit instructs the restoration in response to the internal control signal.
Thus, the internal control signal accurately reflecting level transition of the external control signal can be produced even in the low power consumption mode, enabling reliable restoration from the low power consumption mode to the normal mode.
Preferably, the internal power supply circuit further includes a buffer portion provided between the reference voltage generation portion and the internal power supply voltage generation portion, for transmitting the reference voltage from the reference voltage generation portion to the internal power supply voltage generation portion, and a second current shut-off switch for shutting off an operating current of the buffer portion in the low power consumption mode.
Since the reference voltage is thus transmitted to the internal power supply voltage generation portion through the buffer portion, variation in reference voltage due to noise or the like can be suppressed.
Preferably, the buffer portion includes an operating current control portion for controlling an operating current amount. The operating current control portion sets the operating current amount in a transition period from the low power consumption mode to the normal mode to a larger value than that in the normal mode.
In particular, in such a structure, the reference voltage generation portion sets the reference voltage to the second external power supply voltage in the low power consumption mode, and the transition period corresponds to a period during which the reference voltage is at a prescribed level or less.
Thus, the reference voltage can rise quickly upon restoration from the low power consumption mode to the normal mode, enabling rapid restoration of the internal power supply voltage.
According to another aspect of the invention, a semiconductor memory device capable of switching a level of an external power supply voltage includes: an internal circuit for conducting a data read operation, a data write operation and a data hold operation; an external power supply line receiving the external power supply voltage; an internal power supply line for transmitting an internal power supply voltage to the internal circuit; and an internal power supply circuit for receiving the external power supply voltage and supplying an internal power supply current to the internal power supply line so as to keep the internal power supply voltage at a target level. The operation of supplying the internal power supply current in the internal power supply circuit is switched according to the level of the external power supply voltage in order to maintain the same control response of the internal power supply voltage regardless of the level of the external power supply voltage.
Since the operation of supplying the internal power supply current is switched according to the level of the external power supply voltage, the control response of the internal power supply voltage can be maintained regardless of the level of the external power supply voltage.
Preferably, the internal power supply circuit includes a reference voltage generation portion for receiving the external power supply voltage and generating a reference voltage corresponding to the target level, a voltage comparison portion for producing a voltage at an internal node according to a comparison result between the reference voltage and the internal power supply voltage, and an internal power supply current supplying portion provided between the external power supply line and the internal power supply line, for supplying the internal power supply current to the internal power supply line with the same current supplying capability regardless of the level of the external power supply voltage. When the level of the external power supply voltage is higher than the target level, the internal power supply current supplying portion supplies the internal power supply current according to the voltage at the internal node, and in an external power supply voltage direct-coupling mode in which the level of the external power supply voltage corresponds to the target level, the internal power supply current supplying portion electrically couples the external power supply line to the internal power supply line so as to supply the internal power supply current.
In particular, in such a structure, the internal power supply current supplying portion includes a first driver transistor provided between the external power supply line and the internal power supply line, for supplying a current corresponding to the voltage at the internal node to the internal power supply line as the internal power supply current, a second driver transistor turned ON in the external power supply voltage direct-coupling mode, for electrically coupling the external power supply line to the internal power supply line, and a connection switch tuned ON in the external power supply voltage direct-coupling mode, for electrically coupling a voltage for turning ON the first driver transistor to the internal node.
Thus, even when the semiconductor memory device has the external power supply voltage direct-coupling mode in which the external power supply line is directly connected to the internal power supply line so as to supply the internal power supply voltage, control response of the internal power supply voltage can be maintained regardless of the level of the external power supply voltage.
Preferably, the internal power supply circuit includes a reference voltage generation portion for receiving the external power supply voltage and generating a reference voltage corresponding to the target level, a voltage comparison portion for producing a voltage at an internal node according to a comparison result between the reference voltage and the internal power supply voltage, a current shut-off switch for shutting off an operating current of the voltage comparison portion when the level of the external power supply voltage corresponds to the target level, a driver transistor provided between the external power supply line and the internal power supply line, for supplying a current corresponding to the voltage at the internal node to the internal power supply line as the internal power supply current, and a connection switch turned ON in an external power supply voltage direct-coupling mode in which the level of the external power supply voltage corresponds to the target level, for electrically coupling a voltage for turning ON the driver transistor to the internal node.
Thus, power consumption in the external power supply voltage direct-coupling mode can be reduced.
Preferably, the internal power supply circuit includes a voltage comparison portion for producing a voltage at a first internal node according to a comparison result between a reference voltage corresponding to the target level and the internal power supply voltage, and an internal power supply current supplying portion provided between the external power supply line and the internal power supply line, for supplying the internal power supply current to the internal power supply line according to the voltage at the first internal node. The internal power supply current supplying portion supplies the internal power supply current with the same current supplying capability regardless of the level of the external power supply voltage.
More preferably, the internal power supply current supplying portion includes a first driver transistor provided between the external power supply line and the internal power supply line, for supplying a current corresponding to the voltage at the first internal node to the internal power supply line as the internal power supply current, a second driver transistor provided between the external power supply line and the internal power supply line, for supplying a current corresponding to a voltage at a second internal node to the internal power supply line as the internal power supply current, a gate circuit for electrically coupling the first and second internal nodes to each other according to the level of the external power supply voltage, and a connection switch tuned ON complementarily to the gate circuit, for electrically coupling a voltage for turning OFF the second driver transistor to the second internal node.
Preferably, the internal power supply circuit includes a voltage comparison portion for producing a voltage at a first internal node according to a comparison result between a reference voltage corresponding to the target level and the internal power supply voltage, a driver transistor provided between the external power supply line and the internal power supply line, for supplying a current corresponding to the voltage at the first internal node to the internal power supply line as the internal power supply current, and a first operating current control portion for switching an operating current amount to be supplied to the voltage comparison portion according to the level of the external power supply voltage.
In such a semiconductor device, in the case where the applied level of the external power supply voltage is higher than the internal power supply voltage, control response of the internal power supply voltage can be maintained even if the level of the external power supply voltage is switched.
More preferably, the internal power supply circuit further includes a second operating current control portion for supplying a prescribed amount of operating current to the voltage comparison portion upon execution of a self-refresh command for conducting the data hold operation. The prescribed amount of operating current is smaller than the operating current amount supplied from the first operating current control portion, and supply of the operating current from the first operating current control portion is discontinued upon execution of the self-refresh command.
Thus, the operating current of the voltage comparison portion is reduced in the execution period of the self-refresh command during which the internal circuit consumes a small amount of current, whereby power consumption can further be reduced.
Preferably, the internal power supply voltage is higher than the external power supply voltage in a normal mode, and the internal power supply voltage includes a first detection portion operating both in an active period and a standby period, for sensing reduction in the internal power supply voltage to a level lower than the target level, a second detection portion operating in the active period, for sensing reduction in the internal power supply voltage to a level lower than the target level, a third detection portion operating in response to a sensing result of the first detection portion in a period other than during execution of a self-refresh command for the internal circuit, for sensing reduction in the internal power supply voltage to a level lower than the target level, a first booster unit operating in response to respective sensing results of the second and third detection portions, for boosting the external power supply voltage so as to supply the internal power supply current, and a second booster unit operating in response to the sensing result of the first detection portion, for boosting the external power supply voltage so as to supply the internal power supply current. The second booster unit is capable of supplying a larger amount of internal power supply current per unit time than the first booster unit.
More preferably, the first booster unit includes an oscillation portion for generating a pump clock having a predetermined cycle in response to the respective sensing results of the second and third detection portions, a pumping portion for setting a voltage at a first node to a value higher than the external power supply voltage in response to the pump clock, a transmission transistor electrically coupled between the first node and the internal power supply line, and a gate boosting portion for setting a gate voltage of the transmission transistor to a value higher than the external power supply voltage in response to the pump clock. The pumping portion includes a first pump capacitor coupled between a second node receiving the pump clock and the first node, a clock transmission circuit rendered in an operating state according to the level of the external power supply voltage, for transmitting the pump clock to a third node, and a second pump capacitor coupled between the first node and the third node.
In particular, the clock transmission circuit is forcibly set to the operating state in response to a signal applied in a test mode.
Preferably, the first booster unit includes a first oscillation portion for generating a first pump clock having a first cycle in response to the respective sensing results of the second and third detection portions, a first pumping portion for setting a voltage at a first node to a value higher than the external power supply voltage in response to the first pump clock, a first transmission transistor electrically coupled between the first node and the internal power supply line, and a first gate boosting portion for setting a gate voltage of the first transmission transistor to a value higher than the external power supply voltage in response to the first pump clock. The second booster unit includes a second oscillation portion for generating a second pump clock having a second cycle longer than the first cycle in response to the sensing result of the first detection portion, a second pumping portion for setting a voltage at a fourth node to a value higher than the external power supply voltage in response to the second pump clock, a second transmission transistor electrically coupled between the fourth node and the internal power supply line, and a second gate boosting portion for setting a gate voltage of the second transmission transistor to a value higher than the external power supply voltage in response to the second pump clock. The first and second gate boosting portions switch a boosting amount from the external power supply voltage according to the level of the external power supply voltage.
In such a semiconductor memory device, in the case where the internal power supply voltage is produced by boosting the external power supply voltage, control response of the internal power supply voltage can be maintained even if the level of the external power supply voltage is switched. More specifically, in this case, the control response of the internal power supply voltage can be maintained by switching the current supplying capability of the first and second booster units according to the level of the external power supply voltage.
Preferably, the first booster unit includes an oscillation portion for generating a pump clock having a predetermined cycle in response to the sensing results of the second and third detection portion and a pumping circuit for supplying the internal power supply current by charge pumping operation with the pump clock. The oscillation portion includes an odd number of inverters coupled in a cyclic manner, and a delay element coupled between the inverters. In particular, the delay element includes a diffused resistor formed on a semiconductor substrate.
Thus, the cycle of the pump clock can be kept stable regardless of the level of the external power supply voltage, whereby disturbance of the control over the internal power supply voltage can be suppressed.
Preferably, the internal power supply circuit includes a connection switch for electrically coupling the external power supply line to the internal power supply line in a low power consumption mode, and a current shut-off switch for shutting off an operating current of the first, second and third detection portions in the low power consumption mode. Thus, power consumption in the low power consumption mode can be reduced.
According to a further aspect of the invention, a semiconductor memory device to which one of a plurality of operating conditions is selectively applied includes an operation test control circuit for instructing, during operation testing, initiation of a prescribed test according to a specific combination of having a plurality of bits of a predetermined signal. The operation test control circuit includes a first test entry circuit for activating a first test entry signal in response to the specific combination, and a test entry overriding circuit for forcibly inactivating the first test entry signal when a specific one of the plurality of operating conditions is designated. The operation test control circuit initiates the prescribed test in response to activation of the first test entry signal.
Thus, whether a specific operating condition has been designated or not can be sensed in a simplified manner by checking if the prescribed test can be initiated in the operation test.
Preferably, the operation test control circuit further includes a second test entry circuit for activating a second test entry signal in response to another combination of the plurality of bits that is different from the specific combination. The operation test control circuit initiates the prescribed test in response to activation of either the first or second test entry signal.
Thus, the prescribed test can be initiated even when the specific operating condition has been designated.
Preferably, each of the operating conditions corresponds to a level of an external power supply voltage to be supplied. Thus, in the case where different levels of external power supply voltages are applicable, whether a specific external power supply voltage has been applied or not can be sensed in a simplified manner.
Preferably, each of the operating conditions corresponds to an amplitude voltage of a signal to be input/output. Thus, in the case where different levels of I/O signals are applicable, whether an I/O signal of a specific voltage level has been applied or not can be sensed in a simplified manner.